The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. As the dimensions of transistors decrease, the thickness of the gate dielectric layer must be reduced to maintain performance with the decreased gate length. However, in order to reduce gate leakage, high dielectric constant (high-k) gate dielectric layers are used which allow greater physical thicknesses while maintaining the same effective thickness as would be provided by a gate dielectric layer used in future technology nodes.
FIGS. 1A-1B show cross-sectional views of a conventional high-k gate dielectric layer 112 of a semiconductor device 100 at various stages of fabrication. FIG. 1A illustrates a high-k gate dielectric layer 112 is formed over a substrate 102. The high-k gate dielectric layer 112 may be formed using an atomic layer deposition (ALD) process. The ALD process comprises a sequence of ALD cycles, with each cycle including a step of introducing a metal source chemical to form a chemi-sorption layer over top surface of the substrate 102, a residual metal source chemical purge step, a step of introducing an oxygen source chemical that reacts with the chemi-sorption layer under suitable temperature and pressure conditions to form a portion of the high-k gate dielectric layer 112, and a residual oxygen source chemical purge step. After the deposition process, vacancies 112a and impurities 112b from both source chemicals are embedded in the high-k gate dielectric layer 112.
And then, an oxygen-containing plasma treatment 180 (shown in FIG. 1B) is performed on the high-k gate dielectric layer 112. During the plasma treatment 180, oxygen radicals in the oxygen-containing plasma may penetrate through the high-k gate dielectric layer 112 to fill the vacancies 112a and replace the impurities 112b in the high-gate dielectric layer 112.
However, problems arise if excess oxygen radicals penetrate through the high-k gate dielectric layer 112 and reach the top surface of the substrate 102, an unwanted silicon oxide 112c may be formed on the top surface of the substrate 102, thereby increasing effective thickness of the high-k gate dielectric layer 112. Thus, the device performance characteristics such as threshold voltage may degrade.
Accordingly, what is needed is a method for fabricating a high-k gate dielectric layer having no unwanted silicon oxide.